Memory Subsystem Design and Integration Engineer Job Listing at AMD in Austin, TX (Job ID 75624-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE

The Memory Subsystem team is seeking experienced RTL design engineers to contribute to the development of high-speed LPDDRx, DDRx, and DDR Subsystems. You will participate in defining, designing, and implementing industry-leading Memory IP and subsystems, including timing and floor planning across multiple product lines. This role involves close collaboration with verification teams to ensure quality and performance.

THE PERSON:
We are seeking engineers who bring strong technical expertise and a collaborative mindset. If you enjoy solving complex engineering challenges and working in a team-oriented environment, we encourage you to apply. The ideal candidate can communicate technical concepts clearly, share knowledge to support team growth, and adapt to dynamic situations with effective problem-solving skills. We value individuals who are committed to delivering high-quality solutions while fostering cooperation across diverse teams.

KEY RESPONSIBILITIES

• Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams
• Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power
• Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
• Knowledge sharing and other contributions to Platform & System Architecture
• As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests
• Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs
• Excellent knowledge of System Verilog and Verilog language with respect to RTL design.
• Advanced DDR subsystem architecture, microarchitecture, development, and implementation experience.
• Excellent debug skills and knowledge of key DDR subsystem components.
• Development and maintenance of DDR Subsystem integration, documentation, timing, and floor planning through the lifecycle of pre-silicon development.
• Subsystem and block level documentation as well as timing diagrams
• In depth knowledge of standard IP interfaces, communication of interfaces, and IP interface protocol and utilization.
• Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware level clocking/CDC

 PREFERRED EXPERIENCE:

• Solid and robust foundation in Systems & SoC architecture, with expertise in Memory sub-system, Fabrics, CI/O subsystems, Clocks, Resets, and Security
• Experience analyzing System-level Micro-Architectural features to identify performance bottlenecks within different workloads
• Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
• Experience with DDR/JEDEC standard IP, DDR PHY, or Memory Controller RTL design and development.
• Knowledge and experience developing SVA/OVL and synthesizable assertions.
• Experience stitching IP to build and design subsystems
• Strong knowledge of Git and perforce.
• UPF experience and knowledge of power supply implementations across subsystems and writing logic and timing constraints to handle clock domain crossings

ACADEMIC CREDENTIALS:

• Bachelor's degree in electrical or computer engineering and relevant experience, or

      Master's or PhD degree in Electrical or Computer Engineering with relevant experience.

LOCATION:

• Austin, TX or Raleigh, NC

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.