Description
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
SENIOR SILICON DESIGN ENGINEER
THE ROLE:
We are seeking a highly motivated and experienced Senior Silicon Design Engineer to join our AECG SIT team. This role involves leading and contributing to the design, integration, and characterization of advanced silicon testchips for FPGA products across cutting-edge process nodes.
THE PERSON:
You are an expert in IC design and manufacturing including analog/digital IP integration, chip design, silicon process or packaging technologies. A good understanding of device physics, reliability and silicon chip manufacturing is essential. The candidate must also demonstrate effective communication, good interpersonal skills, along with a strong interest in emerging technologies and innovation.
KEY RESPONSIBILITIES:
- Facilitate the design and integration of digital and analog IPs within the testchip architecture.
- Develop verification plans and create testbenches to validate chip functionality.
- Generate test patterns to support post‑silicon validation.
- Assist with silicon bring-up, debugging, and lab‑based validation activities.
- Collaborate cross‑functionally with layout designers, IC design teams, foundry partners, CAD engineers, and test teams to ensure smooth integration and execution across all development phases.
PREFERRED EXPERIENCE:
- Good understanding of circuit design, semiconductor device physics, and device reliability.
- Experience in designing and validating circuits across advanced technology nodes, including FinFET and Gate-All-Around (GAA).
- Familiar with digital and custom design and verification flows. Proficient with major EDA tools for RTL coding, circuit simulation, timing closure, parasitic extraction, and physical verification.
- Experience writing comprehensive testbenches and generating test patterns for post‑silicon validation.
- Strong problem‑solving skills with hands-on experience in silicon bring-up and the use of lab bench test equipment.
- Proficient in C/C++ and Python for programming and scripting.
- Familiarity with 2.5D and 3D stacked silicon and advanced packaging technologies is a plus.
- Experience with PCB/package design and signal/power integrity (SI/PI) analysis is a plus.
ACADEMIC CREDENTIALS:
Preferably holds an advanced degree (PhD or MS) in electrical & electronics engineering or physical sciences; alternatively, a bachelor's degree with 5+ years of relevant industry experience is acceptable.
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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