Silicon Design Engineer Job Listing at AMD in San Jose, CA (Job ID 88666-en-us)

Description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.

 

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

THE ROLE:

We are seeking a highly motivated and experienced Silicon Design Engineer to join our AECG SIT team. 

This role focuses on end-to-end RTL-to-GDS implementation of advanced silicon testchips, including place-and-route, timing closure, physical verification, design signoff, and tapeout readiness. The successful candidate will work closely with front-end design, CAD, and silicon validation teams to deliver leading-edge FPGA and ASIC testchip solutions.

 

THE PERSON:

The ideal candidate is a hands-on backend engineer with proven experience owning major portions of the RTL-to-GDS physical implementation flow. You should be comfortable working independently, driving implementation challenges to closure, collaborating across design teams, and delivering successful  tapeouts. Experience in small, fast-moving environments where engineers take broad ownership is highly valued.

 

KEY RESPONSIBILITIES:

• Drive the timing-aware/physical-aware synthesis flow using industry-standard tools (e.g., Design Compiler) to generate optimized netlists.
• Lead the end-to-end digital ASIC/SoC physical design cycle from RTL handoff through GDSII tapeout, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, signal integrity optimization, physical verification, and design signoff.
• Close SoC timing with Static Timing Analysis (STA) using tools such as PrimeTime to validate setup/hold margins across process, voltage, and temperature (PVT) corners.
• Drive tapeout readiness by performing physical signoff analyses including IR drop, electromigration (EM), noise, DRC/LVS verification, and cross-functional reviews with RTL, DFT, package, and foundry teams.
• Assist with post‑silicon bring-up, debugging, and lab‑based validation activities.

 

PREFERRED EXPERIENCE:

• Proven RTL-to-GDS ownership on ASIC/SoC designs, with experience supporting FPGA, adaptive computing, or other high-performance semiconductor products
• Strong experience with physical implementation using Cadence Innovus/Genus and/or Synopsys Fusion Compiler.
• Expertise in place-and-route, timing closure, STA, physical verification, and tapeout signoff.
• Experience with PrimeTime, EMIR analysis, DRC/LVS signoff, and tapeout qualification.
• Successful tapeout experience.
• Experience collaborating with RTL, DFT, CAD, package, and foundry teams.
• Proficiency with Tcl, Python, and shell scripting.
• Experience with silicon bring-up and post-silicon validation is a plus.

 

ACADEMIC CREDENTIALS:

• Preferably holds an advanced degree (PhD or MS) in electrical & electronics engineering or physical sciences; alternatively, a bachelor's degree with several years of relevant industry experience is acceptable.

This role is not eligible for visa sponsorship.

 

#LI-DR2

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD's “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

 Apply on company website