SMTS PERFORMANCE MODELING ENGINEER- Power PERFORMANCE Job Listing at AMD in Bengaluru, KA (Job ID 58270-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

DC-GPU Power Constrained Performance Architect

AMD's Datacenter Performance Group is seeking talented, motivated engineers to drive the Power Constrained Performance of our industry-leading AI/ML/HPC GPUs. The role will involve many aspects of Perf@Power attainment, including pre-Si power modeling, post-Si correlation, workload analysis, setting PPA targets and driving attainment, power/perf roll-ups and reporting, methodology innovations and development. Being passionate about performance and power efficiency is a key ingredient for success in this role.

KEY RESPONSIBILITIES:

• Pre-silicon power modeling (HW-IP, SoC, Multi-GPU nodes/clusters), Power-constrained Performance projections and Reporting
• Pre-silicon PPA target setting (for HW IPs, FW and SW)
• Driving PPA attainment by working with various engineering functions including SOC architecture, System Design, IP Design, Foundry team, Physical Design, Software, Power Management, Post-si validation
• Post Si calibration of models and Power/Performance debug
• Analyzing key workloads for power behaviors and optimization opportunities
• Scripting and coding to automate routine tasks, building new tools for wider usage

KEY QUALIFICATIONS:

• Background in Computer Architecture, Power and Performance
• Experience in Soc Level Power/Performance projections, modeling and optimization
• Experience in power modeling for digital and analog IPs
• Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc..)
• Verilog RTL coding experience/understanding is desirable, especially low power design techniques
• Experience in post-silicon power/performance debug, model correlation  
• Knowledge of DL/ML/LLM workloads will be a bonus
• Fluency in Excel based data analysis & charting, scripting experience in Ruby, Python

EDUCATION:

• Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related

#LI-PK1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.